1. Field of the Invention
This invention relates to improvements in MOS transistors and methods for making same in digital BiCMOS processes, and more particularly to improvements in methods for making isolated, vertical PNP transistors in standard non-oxide-isolated digital BiCMOS twin well DUF (buried layer) processes.
2. Background Information
An accelerating trend in the integrated circuit industry is the merging of analog and digital functions onto the same semiconductor substrate. An example is the integration of analog functions into DSP or other large digital blocks to form complete systems. These so-called "mixed-signal" chips are increasingly built using digital BiCMOS technologies, for a variety of reasons. BiCMOS technologies generally provide optimized low-voltage logic performance, particularly in speed of operation. Most BiCMOS processes now have a variety of components available, which simplifies design. However, most designs are heavily weighted toward digital content.
Most digital BiCMOS processes are based on P type silicon substrates, with the backgates of the NMOS devices being interconnected through the common substrate. The lack of non-isolated NMOS transistors can result in several design problems for mixed-signal circuits. First, there is the confusion over substrate biasing when combining dual-supply analog functions with single-supply digital functions. Secondly, the injection of digital switching noise into sensitive analog nodes via the common substrate is undesirable.
Fully isolated NMOS devices have been demonstrated in analog BiCMOS or LinBiCMOS processes. Typically, however, in such processes, an N+ buried layer is used to form the vertical isolation region, while an annular N well or deep N+ collector region is used for the lateral isolation. An NMOS transistor can then be built in an isolated P type epitaxial layer or island. This technique, however, has drawbacks when used in digital BiCMOS processes. Normally, the epitaxial region is thin, on the order of 1.25 .mu.m, and does not allow sufficient vertical separation between the N+ DUF and the N+ source/drain regions. This may lead to severe punch-through breakdown problems under normal minimal bias.
Other processes for forming isolated NMOS devices have been proposed, as well. Some of such processes use deep N wells for high-voltage devices, but require relatively high temperature processing steps. Such high temperatures are incompatible with digital BiCMOS processes, since the N+ buried layer up-diffusion becomes excessive. This requires that the epitaxial layer be increased, thereby degrading the performance of critical NPN devices.
What is needed is a low-cost method for building isolated NMOS transistors in a digital BiCMOS process without disturbing the existing components. In addition to the ability to isolate a single NMOS transistor, there is also a need to isolate large blocks of digital circuitry without altering the design rules, since often it is necessary to bias the substrate below ground for analog functions.